Cost Effective Soft Error Mitigation in Microprocessors

Device scaling has caused the challenges that processor designers face to evolve significantly in the past. This trend will continue into the future, and reliability is emerging as a significant challenge. In this work, we focus on one aspect of the reliability problem: soft errors. In particular, cost effective mitigation of soft errors in processor microarchitecture. Our investigation begins with deep analysis of how transient faults affect microprocessors. We find that fault masking is prevalent in modern processors and identify portions of processors that are particularly vulnerable to faults. Next, we observe that many soft errors share distinguishing attributes. We leverage those attributes and repurpose already existing microarchitectural components to derive a cost effective soft error mitigation solution, providing significant improvements in reliability. Finally, in this work, pains were taken to include as much detail as possible in the processor model and analysis methodology. We conclude with an examination of how making various approximations in the model and analysis methodology affect the experimental results and conclusions of this and other processor reliability studies.